1. Field of the Invention
The present invention relates to semiconductor memory devices and manufacturing method thereof, and more particularly, to a semiconductor memory device having the surface of one electrode of the capacitor subjected to a corrugation process, and a method of fabricating such a semiconductor memory device.
2. Description of the Background Art
In accordance with increase in the integration density of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the elements used in a semiconductor memory device is further reduced in size. Particularly in a DRAM, the capacitor for storing charge is reduced in size, so that the amount of charge that can be stored in a similar device structure is reduced. Measures for noise generated within a semiconductor substrate is a critical element for the reliability of a DRAM device. Soft error is known as one erroneous operation caused by noise. A small amount of the .alpha.-ray emitted from the package and wiring material of a semiconductor memory device is introduced into the silicon substrate to generate electron-hole pairs. These charges become the noise with respect to the charge stored in a memory cell to alter the stored signal. This is the phenomenon of the commonly known soft error. Introduction of charge from a peripheral circuit is known as another noise. Potential difference is generated between the memory cell portion and the peripheral circuit portion by fluctuation in the power supply voltage, whereby noise charge is introduced into the memory cell.
One effective measures with respect to such noise is to increase the amount of charge that is accumulated. However, in a device structure that is similar to that of a conventional one, the amount of stored charge is reduced in accordance with increase in the integration density and microminiaturization of the DRAM. An approach is proposed to ensure capacitance of the capacitor by applying a cylindrical type or fin type stacked capacitor for the DRAM. Furthermore, increasing the surface area by rendering the surface of the electrode of the capacitor in a corrugated manner to accommodate further microminiaturization has been considered.
A conventional DRAM having the surface of the electrode of a capacitor formed in a corrugated manner will be described with reference to FIG. 31. FIG. 31 is a sectional view of an example of such a conventional DRAM.
Referring to FIG. 31, an element isolation oxide film 2 is selectively formed at a main surface of a silicon substrate 1. MOS transistor 3a, 3b and 3c are formed at an element formation region surrounded by element isolation oxide films 2. MOS transistor 3a includes impurity diffusion layers 5a and 5b that become the source/drain regions, and a gate electrode 4a formed on the main surface of silicon substrate 1 with a gate insulation layer thereunder. MOS transistor 3b includes impurity diffusion layers 5b and 5c, and a gate electrode 4b. MOS transistor 3c includes impurity diffusion layers 5d and 5e, and a gate electrode 4d. A gate electrode 4c of another MOS transistor extends on element isolation oxide film 2.
Sidewall insulation layers 6a, 6b, 6c, 6d, 6e, 6f, 6g and 6h are formed respectively on the sidewalls of gate electrodes 4a, 4b, 4c and 4d. Insulation layers 7a, 7b, 7c and 7d are formed on gate electrodes 4a, 4b, 4c and 4d, respectively.
A first interlayer insulation layer 8 is formed on the main surface of silicon substrate 1 so as to cover gate electrodes 4a-4d. Contact holes 8a and 8b are formed at predetermined positions of first interlayer insulation layer 8. Plug electrodes 9a and 9b are formed in contact holes 8a and 8b, respectively. A bit line 10 is formed on plug electrode 9a. An interconnection layer 11 is formed on plug electrode 9b.
A second interlayer insulation layer 12 is formed so as to cover bit line 10 and interconnection layer 11. Contact holes 12a and 12b are formed so as to pierce second and first interlayer insulation layers 12 and 8. Contact hole 12a reaches impurity diffusion layer 5a. Contact hole 12b reaches impurity diffusion layer 5c.
A plug portion 13a of a capacitor lower electrode 13 is formed in contact hole 12b. A bottom wall portion 13b of capacitor lower electrode 13 is formed above plug portion 13a. A vertical wall portion 13c of capacitor lower electrode 13 is formed so as to be connected to a side surface of bottom wall portion 13b. A plug portion of another capacitor lower electrode is formed in contact hole 12a.
The surfaces of bottom wall portion 13b and vertical wall portion 13c are formed in a corrugated manner. A capacitor dielectric layer 15 is formed to cover this surface. A capacitor upper electrode 16 is formed to cover capacitor dielectric layer 15. A third interlayer insulation layer 17 is formed to cover capacitor upper electrode 16. A contact hole 17a is formed to pass through first, second, and third interlayer insulation layers 8, 12 and 17. An interconnection layer 18d is formed in contact hole 17a. Interconnection layers 18a, 18b and 18c are respectively formed above third interlayer insulation layer 17.
The process of rendering the surface of vertical wall portion 13c and bottom wall portion 13b in a corrugated manner will be described hereinafter. In the present specification, it is defined that the process of rendering the surface of an element in a corrugated manner to become a concave and convex surface is referred to as a corrugated process. This corrugation process is disclosed in, for example, Japanese Patent Laying-Open No. 3-263370. The surface of vertical wall portion 13c and the surface of bottom wall portion 13b can be rendered in a corrugated manner by the method disclosed in this publication.
In order to apply the above-described corrugation process on bottom wall portion 13b and vertical wall portion 13c of capacitor lower electrode 13 to achieve increase in the surface area, bottom wall portion 13b and vertical wall portion 13c must be amorphous.
The corrugation process is carried out at a temperature of approximately 570.degree. C.-590.degree. C., for example. Therefore, plug portion 13a in contact with the main surface of silicon substrate 1 is crystallized during the corrugation process. Bottom wall portion 13b and vertical wall portion 13c are no longer amorphous if the crystallization is effected up to bottom wall portion 13b and vertical wall portion 13c. There was problem of reduction in the increase of the surface area by the corrugation process.